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Published in 2021 at "Electric Power Systems Research"
DOI: 10.1016/j.epsr.2020.106980
Abstract: Abstract DC-offset in the input of the phase-locked loop (PLL) is an emerging problem that causes oscillations in the estimated fundamental grid phase, frequency, and voltage amplitude. The DC-offset rejection in grid synchronization is a…
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Keywords:
locked loop;
phase locked;
loop offset;
phase grid ... See more keywords