Stability Analysis for Fast Settling Switched Digital Phase-Locked Loops (DPLLs)
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DOI: 10.1109/lcsys.2023.3242830
Abstract: In current generation digital phase-locked loop (DPLL) architectures, techniques like gear-shift mechanism and switched phase-detection are employed to achieve better lock time and jitter performance. This letter presents a framework for detailed analysis of the… read more here.
Keywords: loop parameters; phase locked; analysis; stability ... See more keywords