A Reverse-RSSI Logarithmic Power Detector With +35-dBm Maximum Detectable Power in 180-nm CMOS
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DOI: 10.1109/lmwc.2019.2933184
Abstract: This letter presents a CMOS reverse received signal strength indicator (reverse-RSSI) based logarithmic power detector (PD). A capacitor attenuation array and unbalanced source-coupled rectifiers are utilized to constitute the reverse-RSSI architecture, which greatly increases the… read more here.
Keywords: power detector; logarithmic power; reverse rssi; power ... See more keywords