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   Articles with "memory access" as a keyword



The Design of NoC-Side Memory Access Scheduling for Energy-Efficient GPGPUs

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recommendations! Published in 2017 at "International Journal of Parallel Programming"

DOI: 10.1007/s10766-017-0521-2

Abstract: Memory access scheduling schemes, often performed in memory controllers, have a marked impact on alleviating the heavy burden placed on memory systems of GPGPUs. Existing out-of-order scheduling schemes, like FR-FCFS, improve memory access efficiency by… read more here.

Keywords: access scheduling; memory access; noc side; access ... See more keywords

S²RAM: Optimization of SRAM With Memory Access Patterns

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recommendations! Published in 2024 at "IEEE Access"

DOI: 10.1109/access.2024.3369048

Abstract: This paper presents a static sequential-random-access memory (S2RAM) designed to enable low-power and high-performance operations for workloads involving sequential memory accesses. Considering the address configuration and internal operation of column-interleaved SRAM, we propose an optimized… read more here.

Keywords: memory; memory access; access patterns; access ... See more keywords

Multi-Mode QC-LDPC Decoding Architecture With Novel Memory Access Scheduling for 5G New-Radio Standard

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recommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems I: Regular Papers"

DOI: 10.1109/tcsi.2022.3150022

Abstract: As the low-density parity-check (LDPC) code has a powerful error-correcting performance and can achieve high throughput, it is being used in many application areas and recently adopted as a channel coding method in the 5G… read more here.

Keywords: novel memory; memory access; ldpc; access scheduling ... See more keywords

A 10pJ/bit 256b AES-SoC Exploiting Memory Access Acceleration

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recommendations! Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"

DOI: 10.1109/tcsii.2021.3126984

Abstract: Low-cost high-volume Internet of Things sensors require an end-to-end secure private-content exchange. Restricted energy and computing of system-on-a-chip for low-cost sensor applications drive lightweight hardware acceleration of security primitives. A trade-off between power and time… read more here.

Keywords: memory access; acceleration; energy; unit ... See more keywords

Rethinking Parallel Memory Access Pattern in Number Theoretic Transform Design

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recommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"

DOI: 10.1109/tcsii.2023.3260811

Abstract: Number theoretic transform (NTT) is widely applied as a fundamental component of next-generation cryptosystems. This brief introduces a novel high-low interactive memory access pattern for an out-of-place NTT design, which can be configurable in degree… read more here.

Keywords: memory access; number; theoretic transform; design ... See more keywords

Adaptive One Memory Access Bloom Filters

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recommendations! Published in 2022 at "IEEE Transactions on Network and Service Management"

DOI: 10.1109/tnsm.2022.3145436

Abstract: Bloom filters are widely used to perform fast approximate membership checking in networking applications. The main limitation of Bloom filters is that they suffer from false positives that can only be reduced by using more… read more here.

Keywords: bloom; bloom filters; memory access; one memory ... See more keywords

Symmetric 2-D-Memory Access to Multidimensional Data

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recommendations! Published in 2018 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"

DOI: 10.1109/tvlsi.2018.2801302

Abstract: In this paper, we propose a novel memory architecture with the capability of single-cycle row-wise/column-wise accesses. Such an architecture is highly suitable for workloads featuring spatial locality in multiple dimensions, which is a characteristic of… read more here.

Keywords: memory access; access multidimensional; read write; memory ... See more keywords

Optimizing BCPNN Learning Rule for Memory Access

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recommendations! Published in 2020 at "Frontiers in Neuroscience"

DOI: 10.3389/fnins.2020.00878

Abstract: Simulation of large scale biologically plausible spiking neural networks, e.g., Bayesian Confidence Propagation Neural Network (BCPNN), usually requires high-performance supercomputers with dedicated accelerators, such as GPUs, FPGAs, or even Application-Specific Integrated Circuits (ASICs). Almost all… read more here.

Keywords: memory access; learning rule; optimization; access ... See more keywords