Increasing FPGA Accelerators Memory Bandwidth With a Burst-Friendly Memory Layout
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3201494
Abstract: Offloading compute-intensive kernels to hardware accelerators relies on the large degree of parallelism offered by these platforms. However, the effective bandwidth of the memory interface often causes a bottleneck, hindering the accelerator’s effective performance. Techniques… read more here.
Keywords: increasing fpga; fpga accelerators; accelerators memory; burst ... See more keywords
CongraPlus: Towards Efficient Processing of Concurrent Graph Queries on NUMA Machines
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Parallel and Distributed Systems"
DOI: 10.1109/tpds.2019.2899595
Abstract: Graph analytics has been routinely used to solve problems in a wide range of real-life applications. Efficiently processing concurrent graph analytics queries in a multiuser environment is highly desirable as we enter a world of… read more here.
Keywords: memory bandwidth; processing concurrent; concurrent graph; graph ... See more keywords
A Design of 12.8-Gpixels/s Hardware-Efficient Lossless Embedded Compression Engine for Video Coding Applications
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3175889
Abstract: The memory bandwidth has become a design bottleneck in a video coding system, especially for high-end display resolutions. Embedded compression (EC) can efficiently save the memory bandwidth between a video coding system and its frame… read more here.
Keywords: design; memory; compression; video coding ... See more keywords
Memory Bandwidth Efficient Design for Super-Resolution Accelerators With Structure Adaptive Fusion and Channel-Aware Addressing
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2023.3253803
Abstract: State-of-the-art (SOTA) super-resolution (SR) models can generate high-quality images. However, they require a large external memory bandwidth, making it impossible to implement these models on hardware. Although some work has presented different kinds of layer… read more here.
Keywords: fusion; structure adaptive; super resolution; memory ... See more keywords