Eidetic: An In-Memory Matrix Multiplication Accelerator for Neural Networks
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DOI: 10.1109/tc.2022.3214151
Abstract: This paper presents the Eidetic architecture, which is an SRAM-based ASIC neural network accelerator that eliminates the need to continuously load weights from off-chip, while also minimizing the need to go off chip for intermediate… read more here.
Keywords: eidetic memory; memory matrix; accelerator; matrix multiplication ... See more keywords