LAUSR

250 MHz Multiphase Delay Locked Loop for Low Power Applications

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1 Published in 2017 at "International Journal of Electrical and Computer Engineering"

DOI: 10.11591/ijece.v7i6.pp3323-3331

Abstract: Delay locked loop is a critical building block of high speed synchronous circuits. An improved architecture of amixed signaldelay locked loop (DLL) is presented here. In this DLL, delay cell based on single ended differential… read more here.

Keywords: locked loop; power; 250 mhz; delay ... See more keywords