A 28.4–30.5‐Gb/s Reference‐Less Full‐Rate Clock and Data Recovery With Current Mismatch Elimination in 28‐nm CMOS
Sign Up to like & getrecommendations! Published in 2025 at "Microwave and Optical Technology Letters"
DOI: 10.1002/mop.70467
Abstract: This paper reports a full‐rate reference‐less bang‐bang clock and data recovery (BBCDR) circuit with current mismatch elimination functionality. Specifically, a simplified frequency acquisition loop (FAL) based on lock detection (LD) is proposed to achieve efficient… read more here.
Keywords: rate; clock data; mismatch elimination; current mismatch ... See more keywords
A Power Mismatch Elimination Strategy for an MMC-Based Photovoltaic System
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Energy Conversion"
DOI: 10.1109/tec.2018.2819982
Abstract: This paper proposes a power mismatch elimination strategy for a medium-voltage modular multilevel converter (MMC) -based photovoltaic (PV) system. In the MMC-based PV system, each submodule of the MMC is energized by multiple PV generators,… read more here.
Keywords: power mismatch; elimination strategy; mismatch elimination; power ... See more keywords