Alternative Encoding: A Two-Step Transition Reduction Scheme for MLC STT-RAM Cache
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2021.3112638
Abstract: Although multiple-level-cell (MLC) STT-RAM increases data density, it suffers from the two-step transition (TT) issue. It is because hard domain and soft domain of an MLC STT-RAM cell cannot be flipped to the opposite magnetization… read more here.
Keywords: mlc stt; scheme; stt ram;
A Low-Latency and High-Endurance MLC STT-MRAM-Based Cache System
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3169458
Abstract: Spin-transfer torque magnetic random access memory (STT-MRAM) is a promising cache memory candidate due to its high density, low leakage power, and nonvolatility. Multilevel cell (MLC) STT-MRAM can further increase density by storing 2 bits… read more here.
Keywords: mlc stt; latency; stt mram;