A 171 GHz harmonic-mode PLL with − 14.2 dBm output power in 65 nm CMOS
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DOI: 10.1007/s10470-019-01413-1
Abstract: This letter presents a harmonic-mode PLL (H-PLL) that avoids additional multiplication, filtering, and amplification stages and thus results in an area-efficient implementation. A proof-of-concept 57.5-mW 65-nm CMOS PLL prototype operating at 171 GHz provides − 14.2 dBm… read more here.
Keywords: mode pll; pll; harmonic mode; dbm output ... See more keywords