Delay Monitor Circuit and Delay Change Measurement Due to SEU in SRAM-Based FPGA
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DOI: 10.1109/tns.2018.2828785
Abstract: This paper presents a monitor circuit designed for the detection of extra combinational delays in a high-frequency SRAM-based field-programmable gate array (FPGA). Since in most of the SRAM-based FPGAs, more than 90% of the configuration… read more here.
Keywords: monitor circuit; delay; sram based;