Custom Multicache Architectures for Heap Manipulating Programs
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2016.2608861
Abstract: Memory-intensive implementations often require access to an external, off-chip memory which can substantially slow down an field-programmable gate array accelerator due to memory bandwidth limitations. Buffering frequently reused data on chip is a common approach… read more here.
Keywords: hls; multicache; custom multicache; multicache architectures ... See more keywords