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   Articles with "multiple node" as a keyword



Multiple-node basin stability in complex dynamical networks.

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recommendations! Published in 2017 at "Physical Review E"

DOI: 10.1103/physreve.95.032317

Abstract: Dynamical entities interacting with each other on complex networks often exhibit multistability. The stability of a desired steady regime (e.g., a synchronized state) to large perturbations is critical in the operation of many real-world networked… read more here.

Keywords: stability; multiple node; node basin; basin stability ... See more keywords

Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology

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recommendations! Published in 2020 at "IEEE Access"

DOI: 10.1109/access.2020.3008225

Abstract: Multiple-node upsets (MNUs) caused by charge sharing effects are dramatically increasing in advanced nanoscale digital latches. Consequently, the robust latches against MNU cases are increasingly important. Although some existing robust latches are designed to recover… read more here.

Keywords: node upset; latch; multiple node; mnu cases ... See more keywords

Cost Efficient Flip-Flop Designs With Multiple-Node Upset-Tolerance and Algorithm-Based Verifications

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recommendations! Published in 2025 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"

DOI: 10.1109/tcad.2024.3426271

Abstract: This article presents radiation-hardened flip-flop (FF) designs capable of tolerating soft errors, e.g., single-node upsets (SNUs), double-node upsets (DNUs) and multiple-node upsets (MNUs). First, a 2-input FF and a 3-input FF are proposed as the… read more here.

Keywords: multiple node; tolerance; flip flop; flop designs ... See more keywords

Multiple Node Upset-Tolerant Latch Design

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recommendations! Published in 2019 at "IEEE Transactions on Device and Materials Reliability"

DOI: 10.1109/tdmr.2019.2912811

Abstract: This paper proposes a general method for the design of multiple node upset (MNU)-tolerant latches. First, two double node upset (DNU)-tolerant latches and one triple node upset (TNU)-tolerant latch are introduced. These proposed latches are… read more here.

Keywords: tolerant latch; node upset; multiple node; design multiple ... See more keywords

A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design

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recommendations! Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"

DOI: 10.1109/tvlsi.2022.3204827

Abstract: In this article, a high-performance and low-cost single-event multiple-node-upsets resilient (HLMR) latch is proposed in 55-nm CMOS technology. By using eight normal two-input Muller-C-elements (MCEs) and eight clock-gating (CG)-based two-input MCEs, a feedback loop storage… read more here.

Keywords: node upsets; multiple node; low cost; latch ... See more keywords