Articles with "network chip" as a keyword



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An Improved Low-Power Coding for Serial Network-On-Chip Links

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Published in 2020 at "Circuits, Systems, and Signal Processing"

DOI: 10.1007/s00034-019-01231-w

Abstract: In the fast nanosilicon revolution era, network-on-chip (NoC) architecture offers a significant research solution to on-chip multiprocessor-based real-time applications. As the number of cores increases, power consumption of the resources of NoC also increases. Links… read more here.

Keywords: network chip; power; low power; improved low ... See more keywords
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Network adapter architectures in network on chip: comprehensive literature review

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Published in 2019 at "Cluster Computing"

DOI: 10.1007/s10586-019-02924-2

Abstract: Network on Chip (NoC) is a new distributed, scalable, packet switched-based on chip which has been suggested as perfect solution for traditional centralized, non-scalable bus-based systems on chip (SoC) to handle issues like out-of order… read more here.

Keywords: literature; network; network chip; review ... See more keywords
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Silicon photonic terabit/s network-on-chip for datacenter interconnection

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Published in 2017 at "Optical Fiber Technology"

DOI: 10.1016/j.yofte.2017.12.007

Abstract: Abstract Silicon photonic integration is an enabling technology for power- and cost-effective optical interconnects in exascale performance computers and datacenters which require extremely low power consumption and dense integration for a higher interface bandwidth density.… read more here.

Keywords: integration; network chip; silicon; silicon photonic ... See more keywords
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Design of optimised logic interface for network-on-chip architectures

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Published in 2018 at "Electronics Letters"

DOI: 10.1049/el.2018.0302

Abstract: Achievement of low power consumption in the field of network-on-chip (NoC) is a prominent research in recent days. Many works have attempted to improve performance in NoC using architectural and algorithmic models. The researches attempted… read more here.

Keywords: dtsa; network chip; optimised logic; logic interface ... See more keywords
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MMNoC: Embedding Memory Management Units into Network-on-Chip for Lightweight Embedded Systems

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Published in 2019 at "IEEE Access"

DOI: 10.1109/access.2019.2923219

Abstract: With the advent of the Internet-of-Things (IoT) era, the demand for lightweight embedded systems is rapidly increasing. So far, ultra-low power (ULP) processors have been leading the development of lightweight embedded systems. However, as the… read more here.

Keywords: lightweight embedded; embedded systems; memory management; network chip ... See more keywords
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Energy Aware Parallel Scheduling Techniques for Network-on-Chip Based Systems

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Published in 2021 at "IEEE Access"

DOI: 10.1109/access.2021.3063901

Abstract: Minimizing execution time, energy consumption, and network load through scheduling algorithms is challenging for multi-processor-on-chip (MPSoC) based network-on-chip (NoC) systems. MPSoC based systems are prevalent in high performance computing systems. With the increase in computing… read more here.

Keywords: network chip; parallel scheduling; based systems; energy ... See more keywords
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Network-on-Chip Design Guidelines for Monolithic 3-D Integration

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Published in 2019 at "IEEE Micro"

DOI: 10.1109/mm.2019.2937726

Abstract: Monolithic three-dimensional (M3D) integration is viewed as a promising improvement over through-silicon-via-based 3-D integration due to its greater inter-tier connectivity, higher circuit density, and lower parasitic capacitance. With M3D integration, network-on-chip (NoC) communication fabric can… read more here.

Keywords: m3d integration; integration; m3d; network chip ... See more keywords
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Traffic Characterization Based Stochastic Modelling of Network-on-Chip

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Published in 2023 at "IEEE Transactions on Computers"

DOI: 10.1109/tc.2022.3191965

Abstract: The trend towards multi-core and many-core processors has changed the landscape of computers and servers. Now the performance of a microprocessor heavily depends not only on the data path but also on the memory technology… read more here.

Keywords: network chip; mml mml; analytical model; mml ... See more keywords
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An Effective Optimization Algorithm for Application Mapping in Network-on-Chip Designs

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Published in 2020 at "IEEE Transactions on Industrial Electronics"

DOI: 10.1109/tie.2019.2926043

Abstract: The application mapping problem is an NP-hard combinatorial optimization problem in network-on-chip (NoC) design. Applications of size ($n$ $ >$ 30) cannot be solved optimally by an exact algorithm in reasonable time, and the evolutionary… read more here.

Keywords: tex math; optimization; network chip; inline formula ... See more keywords
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A Bio-Inspired Hybrid Thermal Management Approach for 3-D Network-on-Chip Systems

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Published in 2017 at "IEEE Transactions on NanoBioscience"

DOI: 10.1109/tnb.2017.2704280

Abstract: 3-D network-on-chip (NoC) systems are getting popular among the integrated circuit (IC) manufacturer because of reduced latency, heterogeneous integration of technologies on a single chip, high yield, and consumption of less interconnecting power. However, the… read more here.

Keywords: network chip; management approach; thermal management; approach ... See more keywords
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OrthoNoC: A Broadcast-Oriented Dual-Plane Wireless Network-on-Chip Architecture

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Published in 2018 at "IEEE Transactions on Parallel and Distributed Systems"

DOI: 10.1109/tpds.2017.2764901

Abstract: On-chip communication remains as a key research issue at the gates of the manycore era. In response to this, novel interconnect technologies have opened the door to new Network-on-Chip (NoC) solutions towards greater scalability and… read more here.

Keywords: network; network chip; wireless; chip ... See more keywords