nMOS Transistor Location Adjustment for N-Hit Single-Event Transient Mitigation in 65-nm CMOS Bulk Technology
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DOI: 10.1109/tns.2017.2783935
Abstract: Heavy-ion experiments demonstrated that reducing the distance between nMOS transistor and n-well can reduce N-hit (i.e., hit nMOS transistor) single-event transient (SET) pulsewidth. This principle can be applied for radiation-harden-by-design standard cell design without any… read more here.
Keywords: nmos transistor; transistor; single event; event transient ... See more keywords