LAUSR

Design of Robust Latch for Multiple-Node Upset (MNU) Mitigation in Nanoscale CMOS Technology

Sign Up to like & get
recommendations!
1 Published in 2020 at "IEEE Access"

DOI: 10.1109/access.2020.3008225

Abstract: Multiple-node upsets (MNUs) caused by charge sharing effects are dramatically increasing in advanced nanoscale digital latches. Consequently, the robust latches against MNU cases are increasingly important. Although some existing robust latches are designed to recover… read more here.

Keywords: node upset; latch; multiple node; mnu cases ... See more keywords

Low-Power Highly Reliable SET-Induced Dual-Node Upset-Hardened Latch and Flip-Flop

Sign Up to like & get
recommendations!
0 Published in 2019 at "Canadian Journal of Electrical and Computer Engineering"

DOI: 10.1109/cjece.2019.2895047

Abstract: It appears that the relentless pursuit of Moore’s law scaling from one generation of process technology to the next increases circuit vulnerability to single-event transient (SET)-induced double-node upset (SEDU). In this paper, we present a… read more here.

Keywords: node upset; sedu hardened; power; flip flop ... See more keywords

Cost-Effective and Highly Reliable Circuit-Components Design for Safety-Critical Applications

Sign Up to like & get
recommendations!
1 Published in 2022 at "IEEE Transactions on Aerospace and Electronic Systems"

DOI: 10.1109/taes.2021.3103586

Abstract: With the reduction of technology nodes now reaching 2 nm, circuits become increasingly susceptible to external perturbations. Thereby, soft errors, such as single-node-upset (SNU), single-event-transient (SET), double-node-upset (DNU), and even triple-node-upset (TNU), must be considered… read more here.

Keywords: circuit components; node upset; safety critical; critical applications ... See more keywords

Multiple Node Upset-Tolerant Latch Design

Sign Up to like & get
recommendations!
1 Published in 2019 at "IEEE Transactions on Device and Materials Reliability"

DOI: 10.1109/tdmr.2019.2912811

Abstract: This paper proposes a general method for the design of multiple node upset (MNU)-tolerant latches. First, two double node upset (DNU)-tolerant latches and one triple node upset (TNU)-tolerant latch are introduced. These proposed latches are… read more here.

Keywords: tolerant latch; node upset; multiple node; design multiple ... See more keywords

Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments

Sign Up to like & get
recommendations!
1 Published in 2022 at "IEEE Transactions on Emerging Topics in Computing"

DOI: 10.1109/tetc.2020.3025584

Abstract: With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely… read more here.

Keywords: tolerant latch; quadruple node; node upsets; node upset ... See more keywords