Radiation Hardened Latch Designs for Double and Triple Node Upsets
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DOI: 10.1109/tetc.2017.2776285
Abstract: As the process feature size continues to scale down, the susceptibility of logic circuits to radiation induced error has increased. This trend has led to the increase in sensitivity of circuits to multi-node upsets. Previously,… read more here.
Keywords: dnu tolerant; tolerant latch; triple node; node upsets ... See more keywords
Novel Quadruple-Node-Upset-Tolerant Latch Designs With Optimized Overhead for Reliable Computing in Harsh Radiation Environments
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DOI: 10.1109/tetc.2020.3025584
Abstract: With the rapid advancement of CMOS technologies, nano-scale CMOS latches have become increasingly sensitive to multiple-node upset (MNU) errors caused by radiations. First, this paper proposes a novel latch design, namely QNUTL that can completely… read more here.
Keywords: tolerant latch; quadruple node; node upsets; node upset ... See more keywords
A High-Performance and Low-Cost Single-Event Multiple-Node-Upsets Resilient Latch Design
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DOI: 10.1109/tvlsi.2022.3204827
Abstract: In this article, a high-performance and low-cost single-event multiple-node-upsets resilient (HLMR) latch is proposed in 55-nm CMOS technology. By using eight normal two-input Muller-C-elements (MCEs) and eight clock-gating (CG)-based two-input MCEs, a feedback loop storage… read more here.
Keywords: node upsets; multiple node; low cost; latch ... See more keywords