Breaking the Limits in Ternary Logic: An Ultra-Efficient Auto-Backup/Restore Nonvolatile Ternary Flip-Flop Using Negative Capacitance CNTFET Technology
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Access"
DOI: 10.1109/access.2021.3114408
Abstract: Despite the advantages of ternary logic, it has suffered from excessive transistor count and limited noise margin. This work proposes an ultra-efficient nonvolatile ternary flip-flop (FF) based on negative capacitance carbon nanotube field-effect transistors (NC-CNTFETs).… read more here.
Keywords: noise margin; ultra efficient; backup; ternary logic ... See more keywords
Systematic Transistor Sizing of a CNFET-Based Ternary Inverter for High Performance and Noise Margin Enlargement
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Access"
DOI: 10.1109/access.2022.3144981
Abstract: Noise and variation are the two major challenges for the reliability of digital circuits, especially multiple-valued logic (MVL) circuits where the entire voltage range is divided into some narrow zones. In spite of few correct… read more here.
Keywords: ternary inverter; transistor sizing; noise; noise margin ... See more keywords
Compact Analytical Model to Extract Write Static Noise Margin (WSNM) for SRAM Cell at 45-nm and 65-nm Nodes
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Semiconductor Manufacturing"
DOI: 10.1109/tsm.2017.2772341
Abstract: The operation of static random access memory (SRAM) in the subthreshold region reduces both leakage power and access energy. Subthreshold operation is one of the proficient techniques to accomplish low-power and high performance system on… read more here.
Keywords: noise margin; analytical model; sram; model ... See more keywords