Delay Prediction for ASIC HLS: Comparing Graph-Based and Nongraph-Based Learning Models
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DOI: 10.1109/tcad.2022.3197977
Abstract: While high-level synthesis (HLS) tools offer faster design of hardware accelerators with different area versus delay tradeoffs, HLS-based delay estimates often deviate significantly from results obtained from ASIC logic synthesis (LS) tools. Current HLS tools… read more here.
Keywords: nongraph based; learning models; graph based; hls ... See more keywords