A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2021.3109032
Abstract: A wireline receiver consisting of a linear equalizer, a decision-feedback equalizer (DFE), a clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and architecture techniques that afford substantial power savings. Realized… read more here.
Keywords: receiver; nrz receiver; receiver cmos;
A 15-Gb/s Single-Ended NRZ Receiver Using Self-Referenced Technique With 1-Tap Latched DFE for DRAM Interfaces
Sign Up to like & getrecommendations! Published in 2023 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3208280
Abstract: This brief presents a single-ended (SE) receiver (RX) with a self-referenced (SR) technique using sample and hold (S&H) circuits. The proposed RX does not require a reference voltage (VREF) for data recovery by comparing the… read more here.
Keywords: nrz receiver; ended nrz; single ended; receiver using ... See more keywords
A 0.45 pJ/b 24 Gb/s NRZ Receiver Data-Path Using Half-Baud-Rate Duobinary Sampling
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2024.3378282
Abstract: This brief presents a 24 Gb/s NRZ receiver. To achieve an energy-efficient receiver, duobinary sampling with half-baud-rate operation is proposed. The duobinary sampling reduces the power consumption of an analog front-end (AFE) by reducing the… read more here.
Keywords: nrz receiver; inline formula; rate; baud rate ... See more keywords