An offset calibration scheme for on-chip thermal profiling with differential temperature sensors
Sign Up to like & getrecommendations! Published in 2024 at "Analog Integrated Circuits and Signal Processing"
DOI: 10.1007/s10470-024-02285-w
Abstract: This paper introduces an on-chip analog calibration method tailored for differential temperature sensors in thermal monitoring applications. A three-step calibration process is proposed within a two-stage high-gain instrumentation amplifier to compensate for the output voltage… read more here.
Keywords: temperature; differential temperature; chip; offset calibration ... See more keywords
A Two-Way Interleaved 7-b 2.4-GS/s 1-Then-2 b/Cycle SAR ADC With Background Offset Calibration
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2017.2785349
Abstract: This paper presents a 2 $\times $ time-interleaved 7-b 2.4-GS/s 1-then-2 b/cycle SAR ADC in 28-nm CMOS. The process-voltage-temperature sensitivity of a multi-bit SAR architecture has been improved by the proposed 1-then-2 b/cycle scheme with… read more here.
Keywords: offset calibration; adc; cycle; calibration ... See more keywords
A 65 nm 0.08-to-680 MHz Low-Power Synthesizable MDLL With Nested-Delay Cell and Background Static Phase Offset Calibration
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2017.2689029
Abstract: This brief presents a wide frequency-range synthesizable multiplying delay-locked-loop with a proposed nested delay cell. Operating in two different modes, the clock generator synthesizes output frequency that ranges from 80 kHz to 680 MHz. Owing… read more here.
Keywords: offset calibration; delay cell; 680 mhz; delay ... See more keywords