Design of optimised logic interface for network-on-chip architectures
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DOI: 10.1049/el.2018.0302
Abstract: Achievement of low power consumption in the field of network-on-chip (NoC) is a prominent research in recent days. Many works have attempted to improve performance in NoC using architectural and algorithmic models. The researches attempted… read more here.
Keywords: dtsa; network chip; optimised logic; logic interface ... See more keywords