Memory Optimized Hardware Implementation of Open FEC Encoder
Sign Up to like & getrecommendations! Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3180554
Abstract: This brief presents a power and memory-optimized hardware implementation for the open forward error correction (oFEC) encoder proposed for high-speed fiber optical communications. Instead of storing a large amount of previously encoded data in the… read more here.
Keywords: memory optimized; optimized hardware; hardware implementation; implementation ... See more keywords