A Highly Parallel Hardware Architecture of Table-Based CABAC Bit Rate Estimator in an HEVC Intra Encoder
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Circuits and Systems for Video Technology"
DOI: 10.1109/tcsvt.2018.2830126
Abstract: This paper presents a highly parallel hardware architecture for rate estimation in a High Efficiency Video Coding intra encoder to increase the level of parallelism and reduce the computational time. The adopted rate estimation algorithm… read more here.
Keywords: hardware; hardware architecture; parallel hardware; rate ... See more keywords
Benchmarking Highly Parallel Hardware for Spiking Neural Networks in Robotics
Sign Up to like & getrecommendations! Published in 2021 at "Frontiers in Neuroscience"
DOI: 10.3389/fnins.2021.667011
Abstract: Animal brains still outperform even the most performant machines with significantly lower speed. Nonetheless, impressive progress has been made in robotics in the areas of vision, motion- and path planning in the last decades. Brain-inspired… read more here.
Keywords: benchmarking highly; neural networks; parallel hardware; hardware ... See more keywords