Analysis and Mitigation Methods of Gate Oscillation in Paralleled 10 kV SiC MOSFETs
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DOI: 10.1109/tpel.2025.3554194
Abstract: Gate oscillations exist in paralleled SiC MOSFETs, which can cause false switching behavior and device damage. This article investigates gate oscillations in paralleled 10 kV SiC mosfets as it is currently one of the bottlenecks… read more here.
Keywords: analysis mitigation; paralleled sic; sic mosfets; gate oscillations ... See more keywords