Numerical Investigation of High-Voltage Partial Buried P/N-Layer SOI LDMOS
Sign Up to like & getrecommendations! Published in 2017 at "IEEE Transactions on Electron Devices"
DOI: 10.1109/ted.2017.2724921
Abstract: High-voltage lateral double-diffused MOSFETs with partial buried P/N-type silicon layers (PBPL/PBNL) in silicon-on-insulator (SOI) technology are investigated numerically. In the lateral direction, the partial buried silicon layer (PBL) can introduce an additional electric field peak,… read more here.
Keywords: high voltage; partial buried; layer; pbpl pbnl ... See more keywords
Ultra-Low Specific On-resistance Lateral Double-Diffused Metal-Oxide-Semiconductor Transistor with Enhanced Dual-Gate and Partial P-buried Layer
Sign Up to like & getrecommendations! Published in 2019 at "Nanoscale Research Letters"
DOI: 10.1186/s11671-019-2866-5
Abstract: An ultra-low specific on-resistance (Ron,sp) lateral double-diffused metal-oxide-semiconductor transistor (LDMOS) with enhanced dual-gate and partial P-buried layer is proposed and investigated in this paper. On-resistance analytical model for the proposed LDMOS is built to provide… read more here.
Keywords: buried layer; partial buried; dual gate; resistance ... See more keywords