Advanced Low Pin Count Test Architecture for Efficient Multi-Site Testing
Sign Up to like & getrecommendations! Published in 2020 at "IEEE Transactions on Semiconductor Manufacturing"
DOI: 10.1109/tsm.2020.2994182
Abstract: With the rapidly increasing test time of semiconductor testing, the trend is currently toward improving test parallelism by exploiting multi-site testing. However, excessive test I/O channels and test power consumption lead to the degradation of… read more here.
Keywords: multi site; site testing; test; pin count ... See more keywords