A 1-GS/s 11-Bit SAR-Assisted Pipeline ADC With 59-dB SNDR in 65-nm CMOS
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DOI: 10.1109/tcsii.2018.2814581
Abstract: We present an 11-bit 1-GS/s time-interleaved ( $\times 2$ ) successive approximation register (SAR)-assisted pipeline analog-to-digital converter (ADC) for wideband direct sampling radio-frequency receivers. The proposed ADC architecture combines the speed advantage of the pipeline… read more here.
Keywords: sar assisted; assisted pipeline; pipeline; adc ... See more keywords