A 12-bit High-Speed Time-Interleaved Pipelined Asynchronous Successive-Approximation ADC in 22-nm FDSOI CMOS
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DOI: 10.1109/access.2024.3381037
Abstract: A 12-bit time-interleaved (TI) analog-to-digital converter (ADC) with pipelined successive-approximation (SAR) channels is presented in this paper. The ADC consists of four TI channels, each incorporating a two-stage pipelined asynchronous SAR ADC. To facilitate clock… read more here.
Keywords: successive approximation; time interleaved; pipelined asynchronous; bit ... See more keywords