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1
Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2021.3133829
Abstract: This work presents a single-channel, fully dynamic pipelined-SAR ADC with relaxed architectural tradeoffs thanks to the use of ring amplification and background calibration. It leverages a novel SAR quantizer and narrowband dither injection to achieve…
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Keywords:
adc;
sar adc;
regulation;
background calibration ... See more keywords
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1
Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3196743
Abstract: This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that…
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Keywords:
adc using;
level shifting;
level;
ring amplifier ... See more keywords
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3
Published in 2023 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3222162
Abstract: This article presents a 13-b high-speed pipelined-successive-approximation-register (pipelined-SAR) analog-to-digital converter (ADC). By utilizing the comparator metastability, a tri-state SAR logic is introduced to achieve a fast approximation process. The tri-state SAR outputs three states by…
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Keywords:
state;
open loop;
adc;
tri state ... See more keywords
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1
Published in 2017 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2016.2576468
Abstract: A 10-bit 500-MS/s partial-interleaving pipelined successive approximation register (SAR) analog-to-digital converter (ADC) architecture is presented that implements a full-speed 2-bit/cycle SAR at the front end with interleaved residue MDACs and SAR ADCs at the back…
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Keywords:
interleaving pipelined;
pipelined sar;
partial interleaving;
500 partial ... See more keywords