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Published in 2023 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2022.3209530
Abstract: Many design optimization methods using machine learning (ML) techniques have been investigated to reduce the number of design iterations in the physical design flow. The demand for big data to support ML research has been…
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Keywords:
place route;
machine learning;
route benchmarks;
design ... See more keywords
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Published in 2021 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2021.3105028
Abstract: Today’s analog and mixed-signal (AMS) layout flow requires long manual iterations and does not leverage computing resources for data-driven optimization. This issue is further compounded by the explosion of design rules and layout-dependent effects (LDEs).…
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Keywords:
digital place;
place route;
mixed signal;
using digital ... See more keywords
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Published in 2022 at "IEEE Transactions on Very Large Scale Integration (VLSI) Systems"
DOI: 10.1109/tvlsi.2022.3170325
Abstract: A 12-bit 20-MS/s asynchronous successive approximation register (SAR) analog-to-digital converter (ADC) is presented by using the digital place-and-route (DPR) tools. The macrocells for the capacitive digital-to-analog converter, the bootstrapped switch, and the dynamic comparator are…
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Keywords:
0067 mm2;
adc;
sar adc;
place route ... See more keywords