A Platform of Resynthesizing a Clock Architecture Into Power-and-Area Effective Clock Trees
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DOI: 10.1109/tcad.2019.2949514
Abstract: To trigger events for application-specific data transfer among registers in a multimillion-gate system-on-chip (SoC), various kinds of clock signals, selectively driven by different frequency-dependent sources and/or dividers (DIVs), are usually centralized in one or more… read more here.
Keywords: platform resynthesizing; power area; area effective; power ... See more keywords