A 2–3 GHz Fast-Locking PLL Using Phase Error Compensator
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DOI: 10.1109/tcsii.2021.3138801
Abstract: A fast-locking phase-locked loop (PLL) using the proposed phase error compensator (PEC) is presented. The PEC compensates the accumulated phase error during the frequency acquisition process to enhance the settling time of this PLL. This… read more here.
Keywords: fast locking; pll; phase; pll using ... See more keywords