Era of Sentinel Tech: Charting Hardware Security Landscapes Through Post-Silicon Innovation, Threat Mitigation and Future Trajectories
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Access"
DOI: 10.1109/access.2024.3400624
Abstract: To meet the demanding requirements of VLSI design, including improved speed, reduced power consumption, and compact architectures, various IP cores from trusted and untrusted platforms are often integrated into a single System-on-Chip (SoC). However, this… read more here.
Keywords: security; hardware security; post silicon;
Bit-Flip Detection-Driven Selection of Trace Signals
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2017.2729458
Abstract: Since integrating memory blocks on-chip became affordable, embedded logic analysis has been used extensively for post-silicon validation and debugging. Deciding at design time which signals to be traceable at the post-silicon phase, has been posed… read more here.
Keywords: detection; trace; selection; bit flips ... See more keywords
Post-Silicon Receiver Equalization Metamodeling by Artificial Neural Networks
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2018.2834403
Abstract: As microprocessor design scales to the 10-nm technology and beyond, traditional pre- and post-silicon validation techniques are unsuitable to get a full system functional coverage. Physical complexity and extreme technology process variations severely limits the… read more here.
Keywords: equalization; validation; neural networks; post silicon ... See more keywords
QBF-Based Post-Silicon Debug of Speed-Paths Under Timing Variations
Sign Up to like & getrecommendations! Published in 2018 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2018.2858291
Abstract: Speed-path debugging at the post-silicon stage due to timing variations is a challenging problem in designing high-performance digital circuits. In this paper, we propose an efficient and scalable method for automatic speed-path debugging which is… read more here.
Keywords: speed; timing variations; post silicon; qbf based ... See more keywords
Experts in the Loop: Conditional Variable Selection Based on Deep Learning for Accelerating Post-Silicon Validation
Sign Up to like & getrecommendations! Published in 2024 at "IEEE Transactions on Semiconductor Manufacturing"
DOI: 10.1109/tsm.2024.3373690
Abstract: Post-silicon validation is one of the most critical processes in modern semiconductor manufacturing. Specifically, correct and deep understanding in test cases of manufactured devices is key to enable post-silicon tuning and debugging. This analysis is… read more here.
Keywords: variable selection; silicon validation; post silicon;
Post-silicon nano-electronic device and its application in brain-inspired chips
Sign Up to like & getrecommendations! Published in 2022 at "Frontiers in Neurorobotics"
DOI: 10.3389/fnbot.2022.948386
Abstract: As information technology is moving toward the era of big data, the traditional Von-Neumann architecture shows limitations in performance. The field of computing has already struggled with the latency and bandwidth required to access memory… read more here.
Keywords: post silicon; brain; inspired chips; brain inspired ... See more keywords