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Published in 2018 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2017.2729458
Abstract: Since integrating memory blocks on-chip became affordable, embedded logic analysis has been used extensively for post-silicon validation and debugging. Deciding at design time which signals to be traceable at the post-silicon phase, has been posed…
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Keywords:
detection;
trace;
selection;
bit flips ... See more keywords
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Published in 2019 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2018.2834403
Abstract: As microprocessor design scales to the 10-nm technology and beyond, traditional pre- and post-silicon validation techniques are unsuitable to get a full system functional coverage. Physical complexity and extreme technology process variations severely limits the…
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Keywords:
equalization;
validation;
neural networks;
post silicon ... See more keywords
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Published in 2018 at "IEEE Transactions on Circuits and Systems I: Regular Papers"
DOI: 10.1109/tcsi.2018.2858291
Abstract: Speed-path debugging at the post-silicon stage due to timing variations is a challenging problem in designing high-performance digital circuits. In this paper, we propose an efficient and scalable method for automatic speed-path debugging which is…
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Keywords:
speed;
timing variations;
post silicon;
qbf based ... See more keywords
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Published in 2022 at "Frontiers in Neurorobotics"
DOI: 10.3389/fnbot.2022.948386
Abstract: As information technology is moving toward the era of big data, the traditional Von-Neumann architecture shows limitations in performance. The field of computing has already struggled with the latency and bandwidth required to access memory…
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Keywords:
post silicon;
brain;
inspired chips;
brain inspired ... See more keywords