A Low-Cost Quadruple-Node-Upset Tolerant Latch Design and Recovery Rate Optimization Algorithm
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DOI: 10.1109/taes.2025.3581546
Abstract: With the continuous shrinking of nanoscale complementary metal-oxide-semiconductor (CMOS) technology, the critical charge of circuit nodes has significantly decreased, rendering the nodes highly susceptible to soft errors. In this article, a high-performance single-node-upset recovery memory… read more here.
Keywords: node upset; latch; quad hsrm; recovery ... See more keywords