Mitigating and Tolerating Read Disturbance in STT-MRAM-Based Main Memory via Device and Architecture Innovations
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2018.2878166
Abstract: As an important nonvolatile memory technology, spin transfer torque magnetoresistive RAM (STT-MRAM) is widely considered as a universal memory solution for future processors. Employing STT-MRAM as the main memory offers a wide variety of benefits,… read more here.
Keywords: stt mram; main memory; memory; read disturbance ... See more keywords
A Compile-Time Framework for Tolerating Read Disturbance in STT-RAM
Sign Up to like & getrecommendations! Published in 2021 at "IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems"
DOI: 10.1109/tcad.2020.3023666
Abstract: Spin-transfer torque magnetic random access memory (STT-RAM) is one of the most promising candidates for next-generation on-chip memories. While STT-RAM offers high density, negligible leakage power, and fast access speed, it also suffers from read-disturbance… read more here.
Keywords: read disturbance; framework; stt ram; compile time ... See more keywords
REACT: Read/Write Error Rate Aware Coding Technique for Emerging STT-MRAM Caches
Sign Up to like & getrecommendations! Published in 2019 at "IEEE Transactions on Magnetics"
DOI: 10.1109/tmag.2019.2905523
Abstract: Spin-transfer torque magnetic RAMs (STT-MRAMs) are the most promising alternative for static random-access memories in large last-level on-chip caches due to their higher density and near-zero leakage power. However, the reliability of STT-MRAMs is threatened… read more here.
Keywords: tex math; write failure; read disturbance; inline formula ... See more keywords