Built-In Self-Test of High-Density and Realistic ILV Layouts in Monolithic 3-D ICs
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DOI: 10.1109/tvlsi.2022.3228850
Abstract: Nanoscale interlayer vias (ILVs) in monolithic 3-D (M3D) ICs have enabled high-density vertical integration of logic and memory tiers. However, the sequential assembly of M3D tiers via wafer bonding is prone to variability in the… read more here.
Keywords: self test; realistic ilv; high density; test ... See more keywords