A 56-Gb/s 50-mW NRZ Receiver in 28-nm CMOS
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DOI: 10.1109/jssc.2021.3109032
Abstract: A wireline receiver consisting of a linear equalizer, a decision-feedback equalizer (DFE), a clock and data recovery (CDR) circuit, and a demultiplexer (DMUX) employs new circuit and architecture techniques that afford substantial power savings. Realized… read more here.
Keywords: receiver; nrz receiver; receiver cmos;