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Published in 2018 at "Electronics Letters"
DOI: 10.1049/el.2017.3133
Abstract: Speeded up robust features (SURFs) are considered to be the most efficient feature extraction algorithm and it has been implemented in powerful hardware for real-time operation due to its characteristics of data-intensive computation of high…
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Keywords:
descriptor;
reconfigurable hardware;
descriptor extraction;
architecture ... See more keywords
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Published in 2018 at "IEEE Transactions on Automation Science and Engineering"
DOI: 10.1109/tase.2018.2822050
Abstract: This paper deals with the test of a reconfigurable hardware system (RHS). The latter is a hardware device that allows to change the hardware resources at runtime in order to modify the system functions and…
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Keywords:
test;
methodology;
rhs;
methodology efficient ... See more keywords
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Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3144435
Abstract: In this brief, we propose a reconfigurable hardware architecture of successive cancellation (SC) decoder with supporting multiple modes. We also develop three design techniques, including low-area quantization scheme (LA-QS), high-efficient frozen-bit control scheme (HE-FBCS), and…
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Keywords:
hardware architecture;
decoder;
area;
successive cancellation ... See more keywords
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Published in 2022 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2022.3191342
Abstract: Hardware-based neural networks are becoming attractive because of their superior performance. One of the research challenges is to design such hardware using less area to minimize the cost of on-chip implementation. This brief proposes an…
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Keywords:
neural network;
hardware;
fixed layers;
design ... See more keywords
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Published in 2020 at "IEEE Transactions on Network and Service Management"
DOI: 10.1109/tnsm.2020.2964392
Abstract: The Open Computing Language (OpenCL) is increasingly adopted for programming processors with reconfigurable hardware acceleration. The 5G telecommunication infrastructure, imposing strong latency constraints on the managed communications, may benefit from OpenCL-designed accelerated processing. This paper…
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Keywords:
opencl driven;
infrastructure;
reconfigurable hardware;
driven reconfigurable ... See more keywords
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Published in 2018 at "AIAA Journal"
DOI: 10.2514/1.j056382
Abstract: The objective of the present study is to investigate the capability of field-programmable gate array hardware in numerical simulation of a model of a dielectric barrier discharge plasma actuator to accelerate the calculations. The reconfigurable…
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Keywords:
modeling simulation;
plasma;
simulation speed;
hardware ... See more keywords