A 0.25 pJ/bit Data-Rate-Dependent Reconfigurable Receiver With Dual-Mode Divider for Low-Power DDR Memory Interfaces
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DOI: 10.1109/access.2025.3633842
Abstract: This paper presents a data-rate-dependent reconfigurable receiver for low-power DDR (LPDDR) memory interfaces covering data rates of 0.8-to-9 Gb/s. The receiver comprises a clock buffer, a quadrature clock corrector (QCC), a reconfigurable decision feedback equalizer… read more here.
Keywords: reconfigurable receiver; data rate; mode; power ... See more keywords