Performances analysis of reducing router in ring and mesh topology for network-on-chip (NoC) architecture
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DOI: 10.11591/ijeecs.v14.i2.pp802-809
Abstract: The size of the transistor has reached physical processor limitation in particular for traditional bus-based and point-to-point architecture in system-on-chip (SoC). Therefore, network-on-chip (NoC) was proposed as a solution. The performances required for the optimization… read more here.
Keywords: reducing router; router; topology; architecture ... See more keywords