An All-Digital PLL for Cellular Mobile Phones in 28-nm CMOS with −55 dBc Fractional and −91 dBc Reference Spurs
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DOI: 10.1109/tcsi.2018.2855972
Abstract: We propose a time-predictive architecture of an all-digital PLL (ADPLL) for cellular radios, which is optimized for advanced CMOS. It is based on a 1/8-length time-to-digital converter (TDC) of stabilized 7-ps resolution, as well as… read more here.
Keywords: reference spurs; digital pll; dbc; dbc fractional ... See more keywords