A 6.15–10.9 Gb/s 0.58 pJ/Bit Reference-Less Half-Rate Clock and Data Recovery With “Phase Reset” Scheme
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DOI: 10.1109/tcsi.2021.3119907
Abstract: This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge… read more here.
Keywords: clock data; phase; reset scheme; phase reset ... See more keywords