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Published in 2022 at "IEEE Journal of Solid-State Circuits"
DOI: 10.1109/jssc.2022.3196743
Abstract: This article presents a 14-b 130-MS/s two-stage pipelined-SAR analog-to-digital converter (ADC) using a distributed averaging correlated level shifting (DACLS) ring amplifier as its residue amplifier (RA). Compared to the prior CLS and ACLS techniques that…
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Keywords:
adc using;
level shifting;
level;
ring amplifier ... See more keywords