Analytical Models of High-Speed RLC Interconnect Delay for Complex and Real Poles
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DOI: 10.1109/tvlsi.2017.2654921
Abstract: Continuous shrinking of the size of CMOS technology leads to extremely fast devices, but the resulting interconnect structures impose so many parasitic effects that the advantage of extremely scaled and ultrahigh-speed transistors would be completely… read more here.
Keywords: real poles; speed; model; delay ... See more keywords