Transferable Presynthesis PPA Estimation for RTL Designs With Data Augmentation Techniques
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DOI: 10.1109/tcad.2024.3420904
Abstract: In modern VLSI design flow, evaluating the quality of register-transfer level (RTL) designs involves time-consuming logic synthesis using electronic design automation tools, a process that often slows down early optimization. While recent machine learning (ML)… read more here.
Keywords: rtl designs; transferable presynthesis; language; rtl ... See more keywords