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Published in 2020 at "IEEE Transactions on Circuits and Systems II: Express Briefs"
DOI: 10.1109/tcsii.2019.2956101
Abstract: This brief proposes a closed-loop architecture which performs background calibration of time-skew mismatch in time-interleaved ADCs (TIADCs). The proposed scheme is tailored to work with the use of a random sampling sequence (RSS) which can…
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Keywords:
time interleaved;
time;
time skew;
random sampling ... See more keywords