A highly energy-efficient, area-efficient switching scheme for SAR ADC in biomedical applications
Sign Up to like & getrecommendations! Published in 2019 at "Analog Integrated Circuits and Signal Processing"
DOI: 10.1007/s10470-019-01502-1
Abstract: Successive approximation register (SAR) analogue-to-digital converter (ADC) is a good choice for low-power applications owing to its high energy-efficiency. However, in the biomedical applications which require ultra-low power consumption, the existing switching schemes are still… read more here.
Keywords: area; scheme; sar adc; energy ... See more keywords
Energy efficient switching scheme based on MSB-split structure for SAR ADC
Sign Up to like & getrecommendations! Published in 2020 at "Analog Integrated Circuits and Signal Processing"
DOI: 10.1007/s10470-020-01696-9
Abstract: An energy efficient switching algorithm for low voltage SAR ADC is presented. By the combination of MSB-split and merge-and-split techniques, this switching method consumes negative energy in the MSB bit switching, which contributes to 99.76%… read more here.
Keywords: energy efficient; efficient switching; energy; sar adc ... See more keywords
MSB-split VCM-based charge recovery symmetrical switching with set-and-down asymmetrical switching method for dual-capacitive arrays SAR ADC
Sign Up to like & getrecommendations! Published in 2021 at "Analog Integrated Circuits and Signal Processing"
DOI: 10.1007/s10470-020-01789-5
Abstract: With the advanced development of CMOS manufacturing process, the capacitive-array in the successive approximation register analog-to-digital converters (SAR ADCs) has become the dominant source of energy consumption and silicon area. This requires an immediate attention… read more here.
Keywords: dual capacitive; switching method; capacitive arrays; sar adc ... See more keywords
Statistical estimator for simultaneous noise and mismatch suppression in SAR ADC
Sign Up to like & getrecommendations! Published in 2017 at "Electronics Letters"
DOI: 10.1049/el.2017.0928
Abstract: A statistical estimator based on maximum-likelihood estimation theory is developed to simultaneously reduce capacitor mismatch and noise in a successive approximation register analogue-to-digital converter (SAR ADC). After the SAR ADC has finished quantisation, the residue… read more here.
Keywords: estimator; sar adc; noise; mismatch ... See more keywords
160 MS/s 20 MHz bandwidth third-order noise shaping SAR ADC
Sign Up to like & getrecommendations! Published in 2017 at "Electronics Letters"
DOI: 10.1049/el.2017.3969
Abstract: This Letter proposes an operational-amplifier free with an embedded passive gain technique to implement an oversampling, noise shaping successive approximation register (SAR) ADCs. In the proposed scheme, the comparator noise, quantisation noise, settling errors and… read more here.
Keywords: order noise; third order; sar adc; noise ... See more keywords
12 b 50 MS/s 0.18 μm CMOS SAR ADC based on highly linear C‐R hybrid DAC
Sign Up to like & getrecommendations! Published in 2020 at "Electronics Letters"
DOI: 10.1049/el.2019.3141
Abstract: A 12 b 50 MS/s successive-approximation register (SAR) ADC with a highly linear C-R hybrid DAC is presented. The proposed DAC significantly reduces the required total number of unit capacitors by processing the upper bits… read more here.
Keywords: dac; range; sar adc; linear hybrid ... See more keywords
Reusing Charge Injection Cells in SAR ADC for Offset Cancellation
Sign Up to like & getrecommendations! Published in 2025 at "Electronics Letters"
DOI: 10.1049/ell2.70500
Abstract: A digital calibration method is presented to reduce SAR ADC offset mismatch. By reusing charge injection (CI) cells, the offset in the sense amplifier (SA) is reduced to less than 1 LSB. In addition, four… read more here.
Keywords: charge injection; reusing charge; injection cells; sar adc ... See more keywords
A 12-bit 30 MS/s SAR ADC in 180 nm CMOS for PMT signal readout
Sign Up to like & getrecommendations! Published in 2021 at "Journal of Instrumentation"
DOI: 10.1088/1748-0221/16/06/p06002
Abstract: Photomultiplier Tubes (PMTs) are widely used as the photon detector in high energy physics experiments for their fast response and high sensitivity. High precision charge measurement is usually required for PMT readout, and especially in… read more here.
Keywords: adc 180; 180 cmos; readout; sar adc ... See more keywords
A 12-bit 20 MS/s SAR ADC for the readout of HFRS-TPC
Sign Up to like & getrecommendations! Published in 2025 at "Journal of Instrumentation"
DOI: 10.1088/1748-0221/20/08/t08001
Abstract: This paper presents the design and implementation of a 12-bit, 20 MS/s successive approximation register (SAR) Analog-to-Digital Converter (ADC) chip, specifically tailored for the readout of the High-Energy FRagment Separator (HFRS) time projection chamber (TPC)… read more here.
Keywords: bit; logic; hfrs; bit sar ... See more keywords
Ultra-low-power time-efficient circuitry of dual comparator/amplifier for SAR ADC by CMOS technology
Sign Up to like & getrecommendations! Published in 2020 at "Circuit World"
DOI: 10.1108/cw-09-2019-0127
Abstract: Successive approximation register (SAR) analogue to digital converter (ADC) is well-known with regard to low-power operations. To make it energy-efficient and time-efficient, scientists are working for the last two decades, and it still needs the… read more here.
Keywords: sar adc; circuitry; comparator; low power ... See more keywords
Integrating SAR-ADC in GaN-Based Totem Pole PFC: A Step Toward Smart Power Conversion
Sign Up to like & getrecommendations! Published in 2025 at "IEEE Access"
DOI: 10.1109/access.2025.3594333
Abstract: This research investigates whether Successive Approximation Register Analog-to-Digital Converters (SAR-ADCs) might be included in (PFC) converters constructed to improve control precision and power conversion efficiency. The suggested approach enhances real-time voltage and current measurement using… read more here.
Keywords: gan based; power conversion; smart power; sar adc ... See more keywords