A Configurable 10T SRAM-Based IMC Accelerator With Scaled-Voltage-Based Pulse Count Modulation for MAC and High-Throughput XAC
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DOI: 10.1109/tnano.2023.3269946
Abstract: This work proposes a 10T SRAM-based in-memory computation (IMC) architecture that can be configured to perform linear multiply-and-accumulate (MAC) operations and high-throughput XNOR-and-accumulate (XAC) operations. The IMC-MAC operation is performed by using the proposed scaled-voltage-based… read more here.
Keywords: imc; xac; scaled voltage; mac ... See more keywords