Verification of Scheduling of Conditional Behaviors in High-Level Synthesis
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DOI: 10.1109/tvlsi.2020.2978242
Abstract: High-level synthesis (HLS) technique translates the behaviors written in high-level languages like C/C++ into register transfer level (RTL) design. Due to its complexity, proving the correctness of an HLS tool is prohibitively expensive. Translation validation… read more here.
Keywords: method; level; verification scheduling; level synthesis ... See more keywords